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Verification Engineer

San Diego, CA. Posted 10 months ago

logicbulls
Posted By
Shekhar Sasane
Duration
12 Months
Start Date
Within 20 days
Tech Category
Other
Pay
$40 - $100 Hourly, Negotiable
Experience
3 - 10 Years
Tech Sub-Category
Other
Work Permit
Canadian Citizen, EAD, Green Card Holder, TN Permit Holder, US Citizen are encouraged to apply
Tax Terms
N/A

Job Description

Design Verification Engineer

San Diego, CA

Overview:

Design Verification of memory subsystems, DDR based subsystems, knowledge of UVM, system verilog, formal, python, assertions, constraint random test development, coverage generation and analysis. Experience with LPDDR and DDR-PHY is a plus. Participate in verification of advanced memory controller verification. Development of TestBench components in uvm frame work. Develop constraint random test cases using uvm framework, systemverilog. Participate in detailed testing and coverage development of memory controller. Develop directed tests. Analyze corner cases with design team. Develop assertions and formal properties. Develop utitlity and analysis tools in python. Participate in functional and code coverage closure.

 

Qualification Required:

5yrs experience in UVM, system verilog, formal verification, python, assertions, constraint random test development, coverage generation and analysis. Verificatoin methodologies. Experience with LPDDR and DDR-PHY is a plus.

Key Skills
uvm asic rtl rf engineering ddr system verilog formal verification python constraint random test development ddr based subsystems frame work test cases framework systemverilog testing design team analysis tools in python code coverage closure

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