Verification Engineer

Design Verification Engineer

San Diego, CA

Overview:

Design Verification of memory subsystems, DDR based subsystems, knowledge of UVM, system verilog, formal, python, assertions, constraint random test development, coverage generation and analysis. Experience with LPDDR and DDR-PHY is a plus. Participate in verification of advanced memory controller verification. Development of TestBench components in uvm frame work. Develop constraint random test cases using uvm framework, systemverilog. Participate in detailed testing and coverage development of memory controller. Develop directed tests. Analyze corner cases with design team. Develop assertions and formal properties. Develop utitlity and analysis tools in python. Participate in functional and code coverage closure.

Qualification Required:

5yrs experience in UVM, system verilog, formal verification, python, assertions, constraint random test development, coverage generation and analysis. Verificatoin methodologies. Experience with LPDDR and DDR-PHY is a plus.